II.
Workflow overview
Reference · liveworkflow:signal-integrity-analysis
Signal Integrity Analysis overview
Analyzes signal integrity for high-speed digital interfaces -- running IBIS/SPICE simulations for eye diagram compliance, validating transmission line impedance matching, checking crosstalk budgets on adjacent traces, verifying DDR/PCIe/USB timing margins, and confirming EMI compliance through pre-layout and post-layout simulations. Excludes PCB routing decisions.
Attributes
displayName
Signal Integrity Analysis
workflowKind
governance
triggerType
event-driven
typicalCadence
per-revision
complexity
single-team
description
Analyzes signal integrity for high-speed digital interfaces --
running IBIS/SPICE simulations for eye diagram compliance, validating
transmission line impedance matching, checking crosstalk budgets on
adjacent traces, verifying DDR/PCIe/USB timing margins, and
confirming EMI compliance through pre-layout and post-layout
simulations. Excludes PCB routing decisions.
Outgoing edges
applies_to_domain2
- domain:electrical-engineering·DomainElectrical Engineering
- domain:physics·DomainPhysics
involves_role3
- role:staff-engineer·RoleStaff Engineer
- role:principal-engineer·RolePrincipal Engineer
- role:performance-profiler·RolePerformance Profiler
performed_by_org_unit2
- org-unit:engineering·OrgUnitEngineering
- org-unit:research-engineering·OrgUnitResearch Engineering
requires_skill_area2
- skill-area:hardware-abstraction-layer·SkillAreaHardware Abstraction Layer Design
- skill-area:performance-testing·SkillAreaPerformance Testing
triggers_responsibility2
- responsibility:performance-budget-tracking·ResponsibilityPerformance budget tracking
- responsibility:review-architecture-changes·ResponsibilityReview architecture changes
Incoming edges
None.